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Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2019054300
Kind Code:
A
Abstract:
To provide a semiconductor device having a gate insulation film with high breakdown voltage.SOLUTION: A semiconductor device of an embodiment comprises: a SiC substrate; a SiC layer which is provided on the SiC substrate and has a trench extending from a surface toward the SiC substrate; first conductivity type first SiC regions provided in the SiC layer; a second conductivity type second SiC region provided between the first SiC region and the SiC substrate; a first conductivity type third SiC region provided between the second SiC region and the SiC substrate; a gate insulation film provided on lateral faces and a bottom face of the trench; and a gate electrode provided on the gate insulation film. A boundary between the second SiC region and the third SiC region contacts the lateral faces of the trench; and the boundary has a first region and a distance from a surface of the SiC layer increases with increasing distance from the trench; and a distance between a virtual plane which includes an end of the gate electrode on the bottom face side and is parallel to a surface and the second SiC region is larger than half a distance between the third SiC region and the first SiC region.SELECTED DRAWING: Figure 1

Inventors:
OHASHI TERUYUKI
IIJIMA RYOSUKE
Application Number:
JP2019003427A
Publication Date:
April 04, 2019
Filing Date:
January 11, 2019
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L29/78; H01L21/336; H01L29/12; H01L29/739
Domestic Patent References:
JP2009260253A2009-11-05
JP2010098326A2010-04-30
JP2013201361A2013-10-03
JP2012178536A2012-09-13
JP2001339063A2001-12-07
JP2015056542A2015-03-23
JP2012164707A2012-08-30
JP2013093560A2013-05-16
JP2013214568A2013-10-17
Foreign References:
US20120049902A12012-03-01
Attorney, Agent or Firm:
Tetsuma Ikegami
Akira Sudo
Masahiro Takashita