Title:
半導体集積回路装置
Document Type and Number:
Japanese Patent JP3607760
Kind Code:
B2
Abstract:
An integrated circuit device equipped with a test circuit includes a plurality of input/output terminals, an input terminal, and an internal circuit for receiving input data via the plurality of input/output terminals and outputting output data. The test circuit permits data exchange among the input/output terminals, the input terminal and the internal circuit. The test circuit preferably operates in a normal mode to supply input data to the internal circuit through the input/output terminals, and supply output data from the internal circuit through the input/output terminals. The test circuit further operates in a test mode to supply test input data to the internal circuit through one of the input terminal and the input/output terminals. The test circuit further supplies test output data that is output from the internal circuit to one of the input terminal and the input/output terminals which differ from the test input data supplied terminal.
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Inventors:
Yasuhiro Yamamoto
Application Number:
JP26592795A
Publication Date:
January 05, 2005
Filing Date:
October 13, 1995
Export Citation:
Assignee:
富士通株式会社
富士通ヴィエルエスアイ株式会社
富士通ヴィエルエスアイ株式会社
International Classes:
G01R31/317; G01R31/3185; G01R31/319; G11C11/401; G11C11/407; G11C29/00; G01R31/28; G11C29/12; (IPC1-7): G11C29/00; G01R31/28; G01R31/3185; G11C11/401; G11C11/407
Domestic Patent References:
| JP2083900A | ||||
| JP7244999A |
Attorney, Agent or Firm:
Hironobu Onda