デュアルパスマルチモード順次記憶素子

Japanese Patent JP5631934

B2

A dual-path, multimode sequential storage element (SSE) is described herein. In one example, the dual-path, multimode SSE comprises first and second sequential storage elements, a data input, a data output, and a selector mechanism. The first and second sequential storage elements each have an input and an output. The data input is coupled to the inputs of both sequential storage elements and is configured to accept data. The data output is coupled to the outputs of both sequential storage elements and is configured to output the data. The selector mechanism is configured to select one of the sequential storage elements for passing the data from the data input to the data output. In one example, the first sequential storage element comprises a pulse-triggered storage element and the second sequential storage element comprises a master-slave storage element.

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マニシュ・ガーグ
ファディ・アデル・ハンダン

JP2012152627A

November 26, 2014

July 06, 2012

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クゥアルコム・インコーポレイテッドＱＵＡＬＣＯＭＭ ＩＮＣＯＲＰＯＲＡＴＥＤ

H03K3/037; G06F15/78; H03K3/356

Masatoshi Kurata
Shigeo Takakura
Makoto Nakamura
Toshihiro Fukuhara
Peak Takashi
Toshiro Shirane
Nobuhisa Nogawa
Yukinaga Yasujiro
Naoki Kono
Sunagawa 克
Iseki Mamoru 3
Tatsushi Sato
Okada Kishi
Mihoko Horiuchi
Masanori Takeuchi

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