Title:
コイン型電気二重層キャパシタの積層並列接続体
Document Type and Number:
Japanese Patent JP6719614
Kind Code:
B2
Abstract:
To provide a lamination parallel connector of a coin-type electric double-layer capacitor, parallely connected by laminating a plurality of unit cells, without using an insulation member.SOLUTION: A lamination parallel connector comprises: a plurality of unit cells in which a coin-type electric double-layer capacitor having an inner can in which a conducive protective film is formed to all bottom surfaces of an inner side contacted to an electrolyte and an outer can is a unit cell; a first connection terminal connecting the plurality of unit cells; and a second connection terminal connecting the plurality of unit cells. The plurality of unit cells is arranged so as to be laminated and direct the inner can to a lower direction. The first connection terminal is connected to a side surface part of the outer can of the odd-numbered unit cell from the lower order, and connects between the odd-numbered unit cell from the lower order with the unit cell located above. The second connection terminal is connected to the side surface part of the outer can of the even-numbered unit cell from the lower order, and connects between the bottom part of the inner can of the lower unit cell, the even-numbered unit cell, and the unit cell located above.SELECTED DRAWING: Figure 2
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Inventors:
Hideharu Onodera
Application Number:
JP2019059714A
Publication Date:
July 08, 2020
Filing Date:
March 27, 2019
Export Citation:
Assignee:
Seiko Instruments Inc.
International Classes:
H01G11/12; H01G11/76; H01G11/78
Domestic Patent References:
| JP2003197475A | ||||
| JP2005272728A | ||||
| JP2010135316A | ||||
| JP2007069376A | ||||
| JP63050118U |
Foreign References:
| WO2013154046A1 |
Attorney, Agent or Firm:
Takashi Kawai
Hitoshi Nakano
Hitoshi Nakano