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Patent Searching and Data


Document Type and Number:
Japanese Patent JPH021429
Kind Code:
B2
Abstract:
The output signals from the first set of delay elements (111' to 114') of n each with a first delay time (τ') are selectively applied to a second set of delay elements (211 to 214) of m each with a second delay time (T") by means of switch (403). The output signals from the said first and said second of delay elements are processed by the indivisual gain controllable circuits (102', 201) and are composed by an adder (105', 204). The gains (a,, a2, ... an; bo, n1, ... bn) of the gain controllable circuits (102', 201) are respectively controlled by output signals from the control voltage generating circuits (102', 201) which are set by the output signals from comparators (104', 203) for comparing the television signal supplied to the input terminal (100') with a reference signal from the reference signal generating circuit (103'), so that the ghost interference in the television receiver can be reduced by a lesser number of delay elements by subtracting the output signals of the adder circuits (105', 203) from the television input signal in subtractor circuits (106', 205).

Inventors:
AZEYANAGI TOMOMITSU
Application Number:
JP18037880A
Publication Date:
January 11, 1990
Filing Date:
December 22, 1980
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H04N5/21