Title:
AUTOMATIC EQUALIZER
Document Type and Number:
Japanese Patent JP2935309
Kind Code:
B2
Abstract:
PURPOSE: To eliminate distortion and to decide a correct code for an NRZ code, a run length limited code receiving the linear distortion and the non-linear distortion of a waveform.
CONSTITUTION: By a subtraction square circuit 1, a difference between input data D0 and estimated input data D1 is squared and a branchmetric D2 is calculated. By an addition comparison selection circuit 2, a pathmetric D3 is calculated from the branchmetric. By a path memory circuit 3, all paths remained are traced back to the past and decided as a final remaining path. When the remaining path is not converged to one, the path having a minimum pathmetric is decided as the final remaining path within the range of a path memory length. By a decision feedback equalizer circuit 5, the estimated input data is generated from postcursor and precursor and stored in a D-flip-flop. By an address control circuit 4, the D-flip-flop storing the estimated input data is selected. By a delay circuit 6, input data is delayed while correct data is being judged.
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Inventors:
ITOI TETSUSHI
Application Number:
JP11559192A
Publication Date:
August 16, 1999
Filing Date:
May 08, 1992
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G11B20/18; G11B20/10; H03H15/00; H03H17/00; H03H21/00; H03M13/23; H04B3/04; (IPC1-7): G11B20/10; H03M13/12
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)