PURPOSE: To suppress the variance of the widths of pulses generated from two or more signals not related in time to each other so as to be minimum by generating the pulse by synthesizing logically the outputs of N-pieces of pulse generation circuits using N-kinds of clocks with different phases from a clock generation circuit.
CONSTITUTION: A separated sync signal is delayed by definite time by a pulse delay circuit 3, and is inputted to a first pulse generation circuit 5 and a second pulse generation circuit 6. In the first pulse generation circuit 5, one clock 1 of the clock generation circuit 4 is inputted to it, and in the second pulse generation circuit 6 too, other clock 2 of the different phase of the clock generation circuit 4 is inputted to it, and the pulse of definite width is generated on the basis of the pulse of the pulse delay circuit 3. A logic circuit 7 synthesizes logically these two signals, and generates a gate pulse. Therefore, because the pulse width varies only by the portion of phase difference between the clock 1 and the clock 2 of the clock generation circuit 4 in any case, the variance of the generated gate pulses can be minimized.
| JPH01191515 | WAVEFORM SHAPER |
| JP2005006170 | DEVICE FOR AUTOMATICALLY ADJUSTING DUTY CYCLE |
YAMAZAKI MASAHIRO
IWASAKI EIJI
