To provide a charge pump circuit in which jitter is reduced in the case of configuring the PLL circuit.

Switches 1-4 are connected in series between a power supply VDD and ground in this order, a capacitor 5 is provided between a series connecting point of the switches 1, 2 and ground and a capacitor 6 is provided between a series connecting point of the switches 3, 4 and ground. The switches 1, 2 are complementarily on/off-controlled and the switches 3, 4 are also complementarily on/off-controlled so as to drive an output 11 through charge/ discharge operations of the capacitors 5, 6. Since the voltage change in the output 11 depends only on the capacitance of the capacitors 5, 6, when the capacitance of the capacitor is selected smaller than an attendant capacitance of the output 11, the change in the output voltage is small and the jitter in the PLL is reduced.