DATA TRANSFER SYNCHRONIZING DEVICE

Japanese Patent JP3645584

B2

PURPOSE: To decrease an error, and to attain synchronous data transfer across an area boundary by using two single stage synchronous FIFO first-in first-out and N-2 stage multistage asynchronous FIFO instead of an N word multistage FIFO memory device.
CONSTITUTION: Data and a writing signal are added to a first FIFO first-in first-out 12. When the writing signal is asserted, FIFO 12, 14, and 16 capture the data of DATAIN in the next rising edge of a clock signal. For example, the FIFO 12 connects an nEMPTY signal with the writing terminal of the following FIFO 14. For example, the FIFO 14 connects an nFULL signal with the reading terminal of the preceding FIFO 12, and connects the DATAOUT of its own (the FIFO 14) with the DATAIN of the following FIFO 16. Thus, serial connection can be attained. At a reception side, a reading signal is asserted, and data are read from the data output so that the data can be read from the second single stage FIFO 16. The data are written by one clock pulse.

JPH10143650	BUFFER CONTROL SYSTEM AND BUFFER CONTROL CIRCUIT
JP2504193	INDUSTRIAL APPLICABILITY: Control device with buffer memory
JPS62182850	BUFFER CONTROL SYSTEM

Joseph H. Steinmetz
Vicente Buoy Cabana

JP1315094A

May 11, 2005

January 11, 1994

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HEWLETT-PACKARD COMPANY
AGILENT TECHNOLOGIES, INC.

G06F5/06; G06F5/08; G06F5/10; G11C7/00; (IPC1-7): G06F5/06

JP2077836A
JP56047981A

US4891788

Shoichi Okuyama
Arihara Koichi
Matsushima Tetsuo
Hideo Ueno

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