Title:
DELAY COMMAND GENERATING SYSTEM USING MEMORY CIRCUIT
Document Type and Number:
Japanese Patent JPS5699510
Kind Code:
A
Abstract:
PURPOSE:To economize the memory capacity by storing the delay time of a command in the memory circuit, and generating the command when the delay time has coincided with the elapsed time of the artificial satellite. CONSTITUTION:The delay time and the command data are stored in the memory circuits 1a and 1b, respectively. And, the delay time data which has been stored is transferred to the delay time setting circuit 10. Subsequently, the contents of the clock counter 13 showing the elapsed time of the artificial satellite are compared with those of the delay time setting circuit 10 by the comparator 14. And, when the delay time has coincided with the elaspsed time, a command data corresponding to its delay time is read out from the memory circuit 1b, and a command is generated. In this way, when only the defined command is stored in the memory circuits 1a, 1b, that will do, and therefore, the memory can be economized.
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Inventors:
NAKAGAWA NOBUO
Application Number:
JP190780A
Publication Date:
August 10, 1981
Filing Date:
January 11, 1980
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G05D1/00; B64G1/24; G05D1/10; (IPC1-7): B64G1/24