PURPOSE: To drive a large capacitive load with a very low power consumption in high speed, without a DC current circuit from a power supply to ground at the output stage of a drive circuit, by setting a phase difference between input signals to two MOS transistors(TRs) of the drive circuit.
CONSTITUTION: VIN is an input signal and VO is an output signal, Q1 is a P channel MOS TR and Q2 is an N channel MOS TR. A and B are signal generating circuits driving MOS TRsQ1, Q2 respectively. The phase is set so that the low potential state of the output signal B of the circuit B includes the low potential state of the output signal A of the circuit A. In setting the phase as shown in Fig. 4, the MOS TRsQ1, Q2 are not conducted at the same time, the drive circuit is limited to charging or discharge to the load capacitor for an arbitrary time.
JP2003224193 | SEMICONDUCTOR DEVICE AND ITS DRIVING METHOD |
WO/1995/033264 | IMPROVED DATA OUTPUT BUFFER |
JP5336635 | Output buffer circuit |