PURPOSE: To obtain the elastic storage circuit that uses one memory to realize a data speed conversion function and a frame phase aligning function.

CONSTITUTION: A write address counter circuit 12 applies frequency division to a line clock (1.5Mck) to obtain a write address to a memory 11 and a read address counter circuit 13 applies frequency division to an in-device clock (2Mck) to generate a read address to the memory 11, an address selector circuit 14 selects the write address or the read address and gives the selected address to the memory 11, and a timing generating circuit 15 generates a write enable signal, a read enable signal to be given to the memory 11 and an address selecting signal given to the address selector circuit 14, a serial/parallel conversion circuit 16 applies serial/parallel conversion to line side serial data and gives the resulting data to the memory 11, and a parallel/serial conversion circuit 17 applies parallel/serial conversion to read data from the memory 11.