Title:
ELECTROLYTIC CAPACITOR AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP3393804
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To facilitate insulating electrodes from an active layer, reduce the parasitic capacitances between pads of the electrodes and buffer layer or Si substrate to improve the high frequency chakacteristics.
SOLUTION: On an Si substrate 4 are formed a GaAs buffer layer 5 of 0.2-2 μm and AlxGa1-xAs(0.9≤x<1) oxide layer 8 of 0.05-5 μ partly projecting like a band to form a mesa slightly smaller than the gate width Wg, having a resistivity of 105 Ωcm or more. Forming the oxide layer 8 on the buffer layer 5 greatly improves the insulation of the Si substrate 4 from an active layer 6 gate electrode 1, resulting in that no current leak to the buffer layer 5 occurs to thereby improve the high frequency characteristics.
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Inventors:
Genichi Ogawa
Application Number:
JP35584697A
Publication Date:
April 07, 2003
Filing Date:
December 24, 1997
Export Citation:
Assignee:
Kyocera Corporation
International Classes:
H01L29/812; H01L21/338; (IPC1-7): H01L21/338; H01L29/812
Domestic Patent References:
| JP59132119A | ||||
| JP1154525A | ||||
| JP9298295A | ||||
| JP7263483A | ||||
| JP955516A |
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