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Title:
FORMATION OF SUPERLATTICE LAYER
Document Type and Number:
Japanese Patent JPH0478129
Kind Code:
A
Abstract:

PURPOSE: To exclude unnecessary deposition of a polycrystalline layer of the same material as a well layer and a barrier layer, by a method wherein, when a superlattice layer is formed, the well layer and the barrier layer are formed by an organic metal molecular beam epitaxial growth method in the state that a specified temperature is applied to a semiconductor substrate.

CONSTITUTION: A dielectric layer 2 is formed on the main surface la of a semiconductor substrate 1. Next, a dielectric layer 2' is formed. Said layer has a plurality of windows 2a' stretching in a stripe type which make the main surface la of the semiconductor substrate 1 face the outside from the dielectric layer 2, and therefore has a plurality of stripe type dielectric layer parts 2b'. By etching treatment using said layer as a mask, a plurality of trenches 3 are formed at positions facing a plurality of the windows 2a' on the main surface la side of the substrate 1 respectively. Well layers 4a and barrier layers 4b are alternately formed in order on the substrate l. A plurality of superlattice layers 4 are formed wherein the well layers 4a and the barrier layers 4b are alternately laminated in order at positions in a plurality of the trenches 4 facing a plurality of the windows 2a' of the dielectric layer 2' respectively.


Inventors:
SUGIURA HIDEO
YAMADA TAKESHI
IGA RYUZO
Application Number:
JP19049090A
Publication Date:
March 12, 1992
Filing Date:
July 20, 1990
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
C30B25/02; C30B29/40; H01L21/203; H01S5/00; (IPC1-7): C30B25/02; C30B29/40; H01L21/203; H01S3/18
Attorney, Agent or Firm:
Shoji Tanaka