Title:
多数のデータパケット信号送受信機を同時に試験する方法
Document Type and Number:
Japanese Patent JP6427500
Kind Code:
B2
Abstract:
A method of testing, such as for a bit error rate (BER), of multiple data packet signal transceivers during which a tester and the data packet signal transceivers exchange sequences of test data packets and summary data packets. The tester provides the test data packets which contain respective pluralities of data bits with respective predetermined bit patterns. Responsive thereto, the data packet signal transceivers provide the summary data packets which contain respective summary data indicative of the number of data bits with the respective predetermined bit patterns that are correctly received by corresponding ones of the data packet signal transceivers.
More Like This:
| JPH0629358 | INTEGRATED CIRCUIT INSPECTING APPARATUS |
| WO/2006/129372 | SEMICONDUCTOR TESTING APPARATUS |
| JP2914346 | [Title of Invention] Semiconductor device |
Inventors:
Orgard, Christian Wolf
Erdgan, Erdem Sirkan
One, Louise
Si, Gwang
Erdgan, Erdem Sirkan
One, Louise
Si, Gwang
Application Number:
JP2015549372A
Publication Date:
November 21, 2018
Filing Date:
October 02, 2013
Export Citation:
Assignee:
LitePoint Corporation
International Classes:
G01R31/28; H04L1/00
Domestic Patent References:
| JP2009218998A | ||||
| JP2010258960A | ||||
| JP6078028A | ||||
| JP2002101121A | ||||
| JP2003215216A | ||||
| JP2005249781A | ||||
| JP2013505639A | ||||
| JP2008530515A |
Foreign References:
| US20050257104 |
Attorney, Agent or Firm:
Hidekazu Miyoshi
Masakazu Ito
Yuko Hara
Kazushi Ohbuchi
Masakazu Ito
Yuko Hara
Kazushi Ohbuchi