Title:
INTEGRATED RADIATOR TILE WITH LOW PROFILE FOR DUAL LINEARLY AND CIRCULARLY POLARIZED BROADBAND PHASED ARRAY
Document Type and Number:
Japanese Patent JP3472204
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain a flat element for a phased array antenna with a low profile employing a compact laminated disk radiator element.
SOLUTION: The radiator tile is provided with a lower dielectric layer 20 having a ground plane 22 and via-transition section 24a, 24b, a coupling circuit layer 30 provided with 90-degree hybrid coupling circuits 30, 32 coupled with the via-transition section 24a, 24b, a balun layer 50 provided with an RF transition section 56 that is coupled with a plurality of RF transition sections 47 selectively connected between lower/upper ground plans 52, 54, a 180-degree hybrid coupling circuit 53 and the coupling circuits 50, 30, 32 and coupled with the 180-degree hybrid coupling circuit 53, and with a layered disk radiator having a plurality of ground via-holes 55, 34, 57, a dielectric pack 62 with an active radiator 64 on the upper face, an upper dielectric layer 60 adjacent to the active radiator 64, a parasitic radiator 66 placed adjacently to the upper dielectric layer 60, and having a couple of stimulation probes 63.
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Inventors:
Kuang M Lee
Allen TS One
Rok Chow
Allen TS One
Rok Chow
Application Number:
JP20674799A
Publication Date:
December 02, 2003
Filing Date:
July 21, 1999
Export Citation:
Assignee:
Raytheon Company
International Classes:
H01Q21/24; H01Q21/06; (IPC1-7): H01Q21/24; H01Q21/06
Domestic Patent References:
| JP10150320A |
Other References:
【文献】米国特許5880694(US,A)
Attorney, Agent or Firm:
Takehiko Suzue (4 outside)
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