Title:
LOGIC CIRCUIT OF LOW POWER CONSUMPTION
Document Type and Number:
Japanese Patent JP3618424
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve the consumption of electric power by connecting an inverter containing a clock to the output of a path transistor TR logic and then connecting a data holding circuit to the output of the inverter.
SOLUTION: An inverter 2 containing a clock is connected to the output of the path TR logic 1, and a data holding circuit 3 is connected to the output of the inverter 2. In such a constitution of connection, the clock input of the inverter 2 doubles as a write control signal against the circuit 3. Then a PMOS TR 21 and NMOS TR 24 attain the function of the inverter 2, and a PMOS TR 22 and an NMOS TR 23 which are controlled in series with each other function as the switches that are closed with the clock input. Furthermore, the circuit 3 can consists of CMOS inverters 31 and 32 and a resistor 33.
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Inventors:
Kazuo Taki
Application Number:
JP26608995A
Publication Date:
February 09, 2005
Filing Date:
September 07, 1995
Export Citation:
Assignee:
AIL Co., Ltd.
International Classes:
H03K17/16; H03K17/687; H03K19/00; H03K19/0948; H03K19/096; (IPC1-7): H03K19/0948; H03K17/16; H03K17/687; H03K19/096
Domestic Patent References:
| JP60236322A | ||||
| JP244915A |
Attorney, Agent or Firm:
Yuzo Agata