Title:
LOW POWER TYPE RAMBUS DRAM
Document Type and Number:
Japanese Patent JP3947923
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a low power type RAMBUS DRAM in which power consumption is reduced by controlling so that upper and lower series/parallel shift blocks are operated independently by a received bank address.
SOLUTION: In this low power RAMBUS DRAM, an upper series/parallel shift section is connected between an upper memory bank section and an input/ output block section. A lower series/parallel shift section is connected between a lower memory bank section and the input/output block section, and an interface logic circuit section generates a signal for selecting the upper or the lower memory bank section by an externally received write-in or read-out instruction. A DLL section generates a clock signal by a signal outputted from the interface logic circuit section. The input/output block section buffers a clock signal generated from the DLL section, and generates a signal controlling selectively operation of the upper/lower series/parallel shift sections.
Inventors:
Guo Zhou
Application Number:
JP2002218970A
Publication Date:
July 25, 2007
Filing Date:
July 26, 2002
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
G11C11/409; G11C11/4096; G11C7/10; G11C7/22; G11C11/407; G11C11/4076; (IPC1-7): G11C11/409; G11C11/407
Domestic Patent References:
| JP2000149549A | ||||
| JP2000048566A |
Attorney, Agent or Firm:
Kyosei International Patent Office
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