Title:
MANUFACTURING PROCESS OF SEMICONDUCTOR
Document Type and Number:
Japanese Patent JPS574140
Kind Code:
A
Abstract:
PURPOSE:To reduce a lateral expansion of etching and prevent a poor bonding by a method wherein a step for forming a through-hole in the inter-layer insulative film in the multi-layer wiring is made to be an etching step having both wet and dry. CONSTITUTION:Opening is made in the oxidation film 2 on a surface of the substrate plate 1, the first wiring 2 composed of Al, for example, is connected to the diffusion layer in the substrate plate 1, then the inter-layer film 4 such as PSG is accumulated on the overall surface of the film. Then, a resist pattern 5 is arranged, the film 4 is etched to a substantial half of a film thickness by applying, for example, buffer fluoric acid liquid. Then, the remaining part of the film 4 is etched up to the wiring 3 under a plasma etching. Thus, the second wiring 6 is formed by aluminum, for example, to make a multi-layer wiring structure. Thereby, a side etching may be reduced, so that the pattern may be made to the finest one, an exposed surface of the first wiring 3 is not changed to a yellow color, so that a poor bonding may be prevented.
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Inventors:
INOUE YOUICHI
Application Number:
JP7820180A
Publication Date:
January 09, 1982
Filing Date:
June 09, 1980
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/3213; H01L21/302; H01L21/306; (IPC1-7): H01L21/302
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