Title:
METHOD OF DETECTING ERROR IN BINARY-ENCODED INFORMATION AND CIRCUIT STORING BINARY-ENCODED INFORMATION
Document Type and Number:
Japanese Patent JPH01316041
Kind Code:
A
Abstract:
PURPOSE: To enable detection and correction of arbitrary 1-bit error in binary coded information and the detection of 2-bit error by providing a 1st parity generator, a memory circuit, a 2nd parity generator and an error detector, etc. CONSTITUTION: Data for the width of 32 bits to be stored in a RAM 61 are inputted through a line 66 to a 1st parity generator 60 and according to a logic function, 12 parity bits are generated from the generator 60 through the exclusive OR(XOR), etc., of related data bits. Next, these 12 parity bits and 32 data bits are inputted to the RAM 61, read out later and outputted to a 2nd parity generator 62 for 44 bits and 12 syndrome bits are generated from the generator 62 and inputted to an error detector 64. Then, at the detector 64, possibility in the generation and correction of errors is discriminated, and the correctable error is corrected and outputted. Thus, the detection and correction of arbitrary 1-bit error in the binary-coded information, and the detection of 2-bit error can be performed.
Inventors:
UIRIAMU SUPENSAA UOORII ZA SAA
EITAN FUENSON
JIEEMUZU AARU UEZAAFUOODO
EITAN FUENSON
JIEEMUZU AARU UEZAAFUOODO
Application Number:
JP5096289A
Publication Date:
December 20, 1989
Filing Date:
March 02, 1989
Export Citation:
Assignee:
ARDENT COMPUTER CORP
International Classes:
G06F11/10; H03M13/00; H04L1/00; (IPC1-7): G06F11/10; H03M13/00; H04L1/00
Attorney, Agent or Firm:
Masaki Yamakawa (3 outside)