To provide a tool for verifying high-level system characteristics.
In order to make the performance of a CMOS sufficiently clear, a custom design method is widely used for the economic design of microprocessors. However, the accuracy of the design is the main problem due to the complexity of the current generation of processors and the necessity of the intervention of manual designers through design processes. Therefore, a verifying tool which symbolically certifies the equivalency between high-level design specifications and the realization of a MOS transistor level is disclosed. The verifying tool applies an effective logic comparing method by which operations on all possible input patterns are suggestively given. The verifying tool inspects the register transfer level(RTL) system model which is normally used currently for the propriety of the realization of functional simulation executed at the RTL level and a transistor for verification.
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DEBUITSUDO POURU RAPOTEIN
AABUINDO SURINIBUASAN
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