To provide a method for manufacturing a laminated device capable of producing the same with a high yield.
The method comprises: a semiconductor wafer preparing step for preparing m sheets of semiconductor wafers ( m is an integer of 3 or more ); a map forming step for forming nondefective unit and a defective unit maps 12A, 12B, 12C, 12D for every semiconductor wafer in m sheets of semiconductor wafers; a combination detecting step for detecting a combination in which the number of defective semiconductor devices 16b included in the semiconductor devices is minimum by selecting and laminating a predetermined number n sheets of semiconductor wafers from the m sheets of semiconductor wafers; a laminated wafer forming step for forming the predetermined number n sheets of semiconductor wafers according the combination of semiconductor wafers detected in the combination detecting step; and a splitting step for splitting the laminated wafer formed in the laminated wafer forming step along a scheduled division line and forming a laminated device in which the predetermined number n sheets of semiconductor devices are laminated.
| WO/2005/038910 | THREE-DIMENSIONAL INTEGRATED CIRCUIT WITH INTEGRATED HEAT SINKS |
| WO/2023/048813 | GLASS SUBSTRATE EMBEDDED PIC TO PIC AND OFF-CHIP PHOTONIC COMMUNICATIONS |
| JPS62122256 | SEMICONDUCTOR DEVICE |
KIM YONG SUK
MAEDA NOBUHIDE
KAWAI AKIHITO
| JP2006269838A | 2006-10-05 | |||
| JP2007081296A | 2007-03-29 |
Kenji Ito