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Title:
METHOD OF MANUFACTURING SEMICONDUCTOR WAFER
Document Type and Number:
Japanese Patent JP2006140187
Kind Code:
A
Abstract:

To provide a method of manufacturing a semiconductor wafer suitable for forming a high-speed semiconductor device in which a lattice relaxation does not generate in an SiGe layer having a strain and the lattice is sufficiently distorted in an SGOI wafer or a GOI wafer.

The method of manufacturing the semiconductor wafer includes the steps of at least performing the epitaxial growth of the Si1-XGeX layer (0<X≤1) on the front surface of a silicon single crystal wafer becoming a bond wafer, forming an ion implantation layer in the interior of the bond wafer by pouring in at lest one kind of hydrogen ion or rare gas ion through the Si1-XGeX layer, sticking the front surface of the Si1-XGeX layer and the front surface of a base wafer through an insulating film, laminating them, then performing an exfoliating treatment for exfoliating in the ion implantation layer, performing bonding heat treating which bonds the laminated surface at temperature higher than the temperature at the time of performing the exfoliating treatment at least, and then removing the Si layer of the exfoliated layer transferred to the base wafer side by the exfoliating.


Inventors:
YOKOGAWA ISAO
AGA KOJI
MITANI KIYOSHI
Application Number:
JP2004326156A
Publication Date:
June 01, 2006
Filing Date:
November 10, 2004
Export Citation:
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Assignee:
SHINETSU HANDOTAI KK
International Classes:
H01L27/12; H01L21/02; H01L21/20; H01L21/265
Domestic Patent References:
JP2001284558A2001-10-12
JP2003017705A2003-01-17
JP2004265975A2004-09-24
JP2004063730A2004-02-26
JPH11121377A1999-04-30
JP2003168789A2003-06-13
Foreign References:
WO2002043153A12002-05-30
WO2004006327A22004-01-15
WO2003046992A12003-06-05
WO2004077553A12004-09-10
WO2003046993A12003-06-05
Attorney, Agent or Firm:
Mikio Yoshimiya