Title:
METHOD OF POLISHING SEMICONDUCTOR WAFER USING DOUBLE SURFACE POLISHER
Document Type and Number:
Japanese Patent JP3791302
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a method of polishing a semiconductor wafer using a double surface polisher for increasing the flatness of the semiconductor wafer by preventing a sagging by polishing at the outer peripheral part of the wafer.
SOLUTION: During polishing, a big difference between a frictional resistance acting on the surface of the silicon wafer W from an upper surface plate 12 side and that acting on the rear surface of the wafer from a lower surface plate 13 side is given comparing with conventional method. This is because a hard foam urethane foam pad 14 and a soft unwoven cloth pad 15 are used for providing different frictional resistance against the wafer W. Each wafer W thus turns in a wafer holding hole 11a at a speed of as high as 0.1 to 1.0 rpm. As a result, even if a defect occurs during the polishing, the turning of the wafer W will not stop. In addition, an unevenly polished amount is hard to occur partly at the outer peripheral part of the wafer. Thus, a sagging by polishing can be suppressed to increase the flatness of the wafer W.
Inventors:
Toru Taniguchi
Ono Isoroku
Ono Isoroku
Application Number:
JP2000163444A
Publication Date:
June 28, 2006
Filing Date:
May 31, 2000
Export Citation:
Assignee:
Sumco inc.
International Classes:
B24B37/08; B24B37/27; B24B37/28; H01L21/304; (IPC1-7): B24B37/04; H01L21/304
Domestic Patent References:
| JP2000042912A | ||||
| JP1127266A |
Attorney, Agent or Firm:
Ichiro Abe
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