集積回路の並行検査の方法、装置及びシステム - Shanghai Core Go Micro Electronics Co., Ltd.

Title:

集積回路の並行検査の方法、装置及びシステム

Document Type and Number:

Japanese Patent JP5765889

Kind Code:

B2

Abstract:

A method, apparatus and system for integrated circuit testing, wherein a plural number of devices under test (DUTs) and a plural number of comparison apparatuses are placed on a common substrate. The DUTs all operate under the same input stimulation and each produce its own operation output. The outputs are compared by the comparison apparatuses to generate comparison characteristics which are used to filter-out the failed devices. This invention lowers the testing cost, shortens time to product mass-production, and lowers the miss rate of failed devices passed as good ones.

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Inventors:

Kenneth Chen Haolin
Koki Kaya
Toki Chi
Atsushi Zhang
Chung Changchun

Application Number:

JP2010063183A

Publication Date:

August 19, 2015

Filing Date:

March 18, 2010

Export Citation:

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Assignee:

Shanghai Core Go Micro Electronics Co., Ltd.

International Classes:

G01R31/28; G01R31/302; H01L21/66; H01L21/822; H01L27/04

Domestic Patent References:

JP2006275835A
JP11204597A
JP2002350513A
JP2002333465A
JP2003156542A
JP2004040103A
JP2009021398A

Foreign References:

WO2008056609A1

Attorney, Agent or Firm:

Seiji Ohno
Koji Morita
Mamoru Suzuki
Shinji Kato
Osamu Tsuda

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