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Title:
MOS SEMICONDUCTOR CIRCUIT
Document Type and Number:
Japanese Patent JPH01101730
Kind Code:
A
Abstract:

PURPOSE: To obtain an MOS semiconductor circuit where an influence due to the swinging of a voltage is small by allowing the area of an input voltage where a P-channel transistor and an N-channel transistor simultaneously go to an ON-condition and an output potential goes to be intermediate between an L and an H to be narrow.

CONSTITUTION: The source of a P-channel transistor 1 constituting a first inverter 7 is connected to a node 12 which is the drain of a P-channel transistor 3 to constitute a second inverter 8 and an N-channel transistor 4. Then, the source of an N-channel transistor 2 of the first inverter 7 is connected to a node 13 which is the drain of a P-channel transistor 5 to constitute a third inverter 9 and an N-channel transistor 6. Thus, by the influence of the second inverter 8 and the third inverter 9, since the area of an input voltage VIN where the P-channel transistor 1 of the first inverter 7 and the N-channel transistor 2 simultaneously go to the ON-condition is allowed to be narrow, the influence given to an output voltage by the fluctuating of the input voltage goes to be small.


Inventors:
HIRASHIMA KAORI
Application Number:
JP25994387A
Publication Date:
April 19, 1989
Filing Date:
October 14, 1987
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H03K17/16; H01L21/8238; H01L27/08; H01L27/092; H03K17/30; H03K19/094; H03K19/0948; (IPC1-7): H01L27/08; H03K17/16; H03K17/30; H03K19/094
Attorney, Agent or Firm:
Masuo Oiwa (2 outside)



 
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