Title:
MULTIPLEX ADDRESS SPECIFIABLE MEMORY DEVICE
Document Type and Number:
Japanese Patent JPS5798189
Kind Code:
A
Abstract:
A multiaddressable highly integrated semiconductor storage is provided, the storage locations of which are addressable by several independent address systems for parallel reading and/or writing. The storage locations are each made up of n storage elements. One storage location consists, for example, of at least two flip-flops which, via coupling elements are connected to associated separate bit and word lines. Each storage location has at least three independently selectable or addressable entry/exit ports permitting the following operations to be executed in parallel: Read word A, read word B, write word C as well as any combination of two or individual ones of those operations. The number of read ports can be increased by providing further address systems and by substituting triple, quadruple, etc., storage cells for a cell pair.
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Inventors:
HORUSUTO HAINTSU BERUGAA
JIIKUFURIIDO KURUTO BUIIDOMAN
JIIKUFURIIDO KURUTO BUIIDOMAN
Application Number:
JP12825081A
Publication Date:
June 18, 1982
Filing Date:
August 18, 1981
Export Citation:
Assignee:
IBM
International Classes:
G11C11/411; G11C8/16; (IPC1-7): G11C7/00; G11C11/40