Title:
NONVOLATILE SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP3537989
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To enhance the reliability of a memory without increasing a write time, an erase time and a consumption current by stopping a write operation and a erase operation in accordance with facts in which the output potential of a boosting circuit becomes low or it becomes high for a period equal to or longer than a prescribed period.
SOLUTION: A control signal outputting circuit 18 outputs an activated control signal C to be activated when the detection signal D of the output of an output potential detecting circuit 17 is outputted for a period equal to or longer than a preliminarily set period to an internal control circuit 12. Then, the circuit 18 is consisting of a delay circuit and an AND gate and the control signal C becomes an H level only when the detection signal D has an H level period equal to or longer than a low potential detection time. As a result, the control signal C is not activated by a pulse shaped detection signal D whose time, is equal to or shorter than the low potential detection time being in an instantaneous potential reduction and it is not informed to the internal control circuit 12 that the output of a boosting circuit 13 is in a low potential state.
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Inventors:
Mori, Yasumichi
Application Number:
JP10283497A
Publication Date:
June 14, 2004
Filing Date:
April 21, 1997
Export Citation:
Assignee:
SHARP CORP
International Classes:
G11C16/02; G11C16/06; (IPC1-7): G11C16/06; G11C16/02
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