To inspect with a repeat of a simple pattern or a less test pattern input by dividing a data latch circuit to one or plural groups, using the data latch circuits of respective bit lines and constituting a shift register at every group.

The data latch circuits 221-223 are constituted of two inverter circuits. A signal inverted on every other piece is inputted to a data transfer circuit. When a data transfer signal CK is in H, the data transfer circuit 212 connecting the mth column data latch circuit 222 with the (m+1)th column data latch circuit 223 is turned on, and the data latched to the mth column data latch circuit 222 are transferred to the (m+1)th column data latch circuit 223. The data latch circuits 221-225 are divided into an odd bit line column group and an even bit line column group, and the shift register is constituted. By only controlling a shift register data transfer signal, the write-in data are fetched to a data latch circuit memory cell.