PURPOSE: To prevent malfunction of an internal integrated circuit due to noise by clamping a signal level fed to a gate of a PMOS and NMOS transistors(TRs) to a prescribed value so as to prevent a large current from flowing to both the TRs thereby suppressing the fluctuation of 1st and 2nd power supplies.

CONSTITUTION: With an input terminal 1 going to 'L', for example from the steady-state where the level of input/output terminals 1, 5 at 'H', since a gate of PMOS and NMOS transistors(TRs) 6, 11 reaches 'H', the TR 6 is turned off and the TR 11 is turned on and an output terminal 5 transits to a low level. Then the gate of NMOS TRs 12∼15 go to 'H' and the TRs 12∼15 are all turned on. Thus, the gate voltage of the TR 11 clamped to a voltage level slightly lower than the power voltage level VDD. Thus, the current flowing to the output TR 11 is reduced more than that when the gate voltage is high suppress the discharge from the load capacitor such as the wiring. Thus, an instantaneous large current flowing to the output TRs 6, 11 is reduced.