To execute a reception sweep operation owing to the frequency deviation of an IF (intermediate frequency) converter in a PLL(phase locked loop) synthesizer type tuner device.

The offset frequency dividing ratio of a programmable frequency divider 24 in the PLL synthesizer 22, which is caused by the frequency deviation of the IF converter 2, is stored in a memory 42 at the time of reception tuning immediately before. At the time of this station selection, CPU 3 sets the offset value of the memory 42 to an offset memory 31 through a switch 43, adds the offset value L to a standard frequency dividing ratio M in an adder 41 and splices (M+L) to the frequency divider 24 as the frequency dividing ratio. When a demodulation identification signal 20 is not supplied at that time, the counting of an up/down counter 37 us started and the frequency is sweep- controlled and automatic tuning is executed so as to sweep the oscillation frequency 15 of the PLL synthesizer 22 within a micro range smaller than the permitted frequency deviation.