Title:
PROCESSOR SYSTEM WITH CACHE MEMORY AND CACHE MEMORY SYSTEM
Document Type and Number:
Japanese Patent JPH1083348
Kind Code:
A
Abstract:
To reduce a mistake caused by contention in a processor system dealing with multimedia data.
A cache memory 2 has its storing area divided into plural blocks in advance to store data in a storing area corresponding to an indicated cache block. CPU 1 indicates a divided cache block ID 16 being identification information of the plural blocks with a memory address 15 at the time of referring to data. A cache access controller 24 generates a cache address from the block ID16 and the address 15 indicated by CPU 1 to refer to data by the cache address.
Inventors:
HOSOKI KOJI
KOJIMA KEIJI
NISHIOKA KIYOKAZU
NOJIRI TORU
FUJIKAWA YOSHIBUMI
EHAMA MASAKAZU
KOJIMA KEIJI
NISHIOKA KIYOKAZU
NOJIRI TORU
FUJIKAWA YOSHIBUMI
EHAMA MASAKAZU
Application Number:
JP23770696A
Publication Date:
March 31, 1998
Filing Date:
September 09, 1996
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G06F12/08; (IPC1-7): G06F12/08; G06F12/08
Attorney, Agent or Firm:
Kazuko Tomita