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Title:
RUSH CURRENT SUPPRESSION CIRCUIT, AND POWER SUPPLY
Document Type and Number:
Japanese Patent JP2014117062
Kind Code:
A
Abstract:

To provide a rush current suppression circuit suppressing the peak of a rush current, and capable of maintaining the gate voltage of a FET around the gate threshold voltage when the power is turned on, and to provide a power supply including the rush current suppression circuit.

A rush current suppression circuit 11 for suppressing a rush current flowing through a smoothing capacitor 9 provided between a power supply 7 and a printer 5 includes a FET 13 for limiting the charging current to the smoothing capacitor 9, a time constant circuit 15 having a capacitor 23 and a resistor 25 and applying a gate voltage, changing with a time constant based on the capacitor 23 and resistor 25, to the gate terminal of the FET 13, and a gate voltage suppression circuit 17 which is connected with the capacitor 23 of the time constant circuit 15, when the gate voltage Vgs exceeds the gate threshold voltage Vgsth, and discharges the capacitor 23 thus suppressing increase in the gate voltage.


Inventors:
TAKEUCHI KAZURO
Application Number:
JP2012269089A
Publication Date:
June 26, 2014
Filing Date:
December 10, 2012
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
H02J1/00; G05F1/10; H02H7/00; H02H9/02; H02M1/00
Attorney, Agent or Firm:
Masahiko Ueyanagi
Kazuhiko Miyasaka
Kazuaki Watanabe



 
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