Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP3533037
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the capacitance of the bit lines of a semiconductor integrated circuit device having DRAM.
SOLUTION: The semiconductor integrated circuit device comprises a DRAM having connection holes 9b1, 9b2a, 9b2b and 9a1 self-matchedly formed to connect semiconductor regions 4b, 4a of memory cell selective MOS FETs 4 to bit lines BL and capacitors 5 by covering the periphery of word lines WL with a silicon nitride cap insulation film 7a and side walls 7b. The bit lines BL are covered with a cap insulation film 11a and side walls 11b, each made of a material having a lower dielectric const. than that of the silicon nitride.
Inventors:
Sekiguchi, Toshihiro
Tadaki, Yoshitaka
Kawakita, Keizo
Aoki, Hideo
Kumai, Toshikazu
Saito, Kazuhiko
Nishimura, Michio
Tanaka, Michio
Yuhara, Katsuo
Nishio, Shinya
Kaeriyama, Toshiyuki
Chiyou, Seishiyu
Tadaki, Yoshitaka
Kawakita, Keizo
Aoki, Hideo
Kumai, Toshikazu
Saito, Kazuhiko
Nishimura, Michio
Tanaka, Michio
Yuhara, Katsuo
Nishio, Shinya
Kaeriyama, Toshiyuki
Chiyou, Seishiyu
Application Number:
JP13553496A
Publication Date:
May 31, 2004
Filing Date:
May 29, 1996
Export Citation:
Assignee:
HITACHI LTD
TEXAS INSTR JAPAN LTD
TEXAS INSTR JAPAN LTD
International Classes:
H01L21/8242; H01L21/60; H01L27/108; (IPC1-7): H01L21/8242; H01L27/108
Attorney, Agent or Firm:
筒井 大和