Title:
SEMICONDUCTOR INTEGRATED CIRCUIT, MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND TEST METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP2001167600
Kind Code:
A
Abstract:
To provide a semiconductor integrated circuit having good quality, a manufacturing method by which such a semiconductor integrated circuit can be manufactured, and a test method.
A semiconductor integrated circuit 1 is provided with a logic circuit 2 connected to external terminals 10-12, a built-in memory 3 connected to this logic circuit, and a burn-in test circuit 4 writing the prescribed data in the built-in memory when a burn-in test of this built-in memory is performed.
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Inventors:
YOSHIZAWA YUTAKA
Application Number:
JP34816099A
Publication Date:
June 22, 2001
Filing Date:
December 07, 1999
Export Citation:
Assignee:
NEC CORP
International Classes:
G01R31/28; G01R31/3187; G11C11/401; G11C11/407; G11C29/02; G11C29/06; G01R31/26; G11C29/08; G11C29/12; H01L21/822; H01L23/544; H01L27/04; (IPC1-7): G11C29/00; G01R31/26; G11C11/407; H01L27/04; H01L21/822
Attorney, Agent or Firm:
Nobuo Takahashi (3 outside)