Title:
半導体集積回路、ブリッジチップ、ディスプレイシステム、自動車
Document Type and Number:
Japanese Patent JP7109272
Kind Code:
B2
Abstract:
An asynchronous FIFO is arranged between an input bus and an output bus with a different number of lanes. The asynchronous FIFO supplies a write clock and a read clock. A circuit block receives output data from the asynchronous FIFO via the output bus, and executes predetermined processing. In a test mode, a test circuit supplies a test pattern as interrupt data to the input bus, and detects the presence or absence of an abnormality based on a relation between the output data and its expected value based on the test pattern.
Inventors:
Kyoichi Murakami
Application Number:
JP2018115465A
Publication Date:
July 29, 2022
Filing Date:
June 18, 2018
Export Citation:
Assignee:
ROHM Co., Ltd.
International Classes:
G01R31/28; H01L21/822; H01L27/04
Domestic Patent References:
| JP2003337161A | ||||
| JP9261692A | ||||
| JP2017053816A | ||||
| JP10082839A | ||||
| JP2002109899A | ||||
| JP2011244218A | ||||
| JP2015226206A | ||||
| JP2007036054A |
Foreign References:
| US10097341 | ||||
| US20030101376 | ||||
| US6816987 | ||||
| US20150102950 | ||||
| US20180332276 | ||||
| US6628324 |
Attorney, Agent or Firm:
Morishita Kenki
Taiki Maya
Taiki Maya
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