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Patent Searching and Data


Title:
SEMICONDUCTOR MEMORY DEVICE AND BURN-IN TEST METHOD
Document Type and Number:
Japanese Patent JPH11328997
Kind Code:
A
Abstract:

To easily achieve shortening of the BT test time by controlling an internal circuit operation only at the time of conducting BT test of a semiconductor memory device having only a synchronous mode burst-operation.

Writing means 4, 9 are arranged to output a write instruction to a memory cell 12 based on a data entry signal DIN, and decoding means 5, 8, 10, 11 are arranged to decode the address input signal and output an address instruction to a memory cell 12. Moreover, a control means 7 outputs a signal to delay decode timing to decoding means 5, 10 based on a control signal 14 inputted at the time of burn-in test. With respect to the operation cycle of the signal by which the write instruction of the writing means 4, 9 is transmitted to the memory cell 12, the operation cycle of the decode timing is delayed and a late write cycle is eliminated.


Inventors:
SUGA KOICHIRO
Application Number:
JP13689198A
Publication Date:
November 30, 1999
Filing Date:
May 19, 1998
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
G11C11/413; G11C29/06; G11C29/50; G01R31/28; (IPC1-7): G11C29/00; G01R31/28; G11C11/413
Attorney, Agent or Firm:
Sugano Naka