Title:
Semiconductor memory device
Document Type and Number:
Japanese Patent JP6151504
Kind Code:
B2
Abstract:
A semiconductor device including a plurality of first diffusion layers that are formed over a semiconductor layer and disposed at predetermined intervals in a first direction, a plurality of second diffusion layers that are formed over the semiconductor layer, isolated from the first diffusion layers in a second direction orthogonal to the first direction, and disposed at the predetermined intervals in the first direction, a plurality of first regions that have a predetermined width in the first direction for separating the first diffusion layers from each other, a plurality of second regions that align with the first regions in the second direction and have the predetermined width for separating the second diffusion layers from each other, and a plurality of contacts that are formed over the first diffusion layers and over the second diffusion layers.
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Inventors:
Hiroyuki Takahashi
Mochimaru Satoshi
Mochimaru Satoshi
Application Number:
JP2012229906A
Publication Date:
June 21, 2017
Filing Date:
October 17, 2012
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/8242; H01L27/108
Domestic Patent References:
| JP8125034A | ||||
| JP2012114274A | ||||
| JP2004087074A | ||||
| JP7135257A |
Attorney, Agent or Firm:
Ken Ieiri
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