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Patent Searching and Data


Title:
SIMULATION METHOD FOR ASSEMBLING LOCUS OF PARTS
Document Type and Number:
Japanese Patent JPH11207669
Kind Code:
A
Abstract:

To easily select an assembling path by selecting parts of near miss states and interference states and correcting the assembling path after a rough carrier path is prepared, parts are carried by a simulation based on this carrier path, near miss states and interference states are calculated and the result is displayed.

In a simulation of an assembling locus, a rough assembling locus is prepared by using an interference function of a graphic simulator at first (S1). Parts are automatically moved based on the prepared assembling locus (S7), the presence or absence of an interference is calculated and the result is listed and displayed (S8). If parts in which an interference occurs exist in this list, the parts are selected (S10). As a result, because the state of the list returns to an interference state (S11), a locus is corrected by a manual operation so as not to generate an interference (S12, S13). Thus, the assembling locus can be efficiently prepared because the defect of an automatic calculation is made up by the manual operation, making the most of the merit of the automatic calculation.


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Inventors:
SHIMAMURA SHIGEO
MOMOSE TETSUO
Application Number:
JP1157198A
Publication Date:
August 03, 1999
Filing Date:
January 23, 1998
Export Citation:
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Assignee:
NISSAN MOTOR
International Classes:
B25J9/22; (IPC1-7): B25J9/22
Attorney, Agent or Firm:
Mikio Hatta (1 outside)