PURPOSE: To shorten a delay time computation time by totalizing propagation delay times according to computation results obtained from plural processors.
CONSTITUTION: A system 1 has the processors 20-23 and circuit information 2 is an information regarding a logic circuit as an object of delay time computation and includes the number of elements constituting the circuit, pieces 31-33 of constituent element information on connections between the respective constituent elements, and information on paths in the circuit. Then, an assignment control part 5 makes usable processors correspond to functional macroprogram as constituent elements of the circuit, generates the necessary number of computation processes 41-43 on the processors, assigns information on the functional macroprograms and refers to the path information, thereby, sending requests for computation to the respective computing processors 41-43. Further, a computation result processing part 6 gathers the computation results of the respective computing processors 41-43 and calculates the delay times of paths in the circuit basing on the information regarding the paths.
| JPH02257218 | ELECTRONIC COMPUTER |
| JPH03232019 | INFORMATION PROCESSOR |
| JPH04123229 | PIPELINE CONTROLLER |
MINODA YORIKO
SAWADA HIDEHO
MARUYAMA FUMIHIRO
