PURPOSE: To attain the addition of a high-speed I/O device or the high-speed operation of the I/O device by varying the scan ratio of each bus-only request given from plural DMA circuits of a bus-only request scan circuit under the control of a processor.

CONSTITUTION: When the I/O device 6n has a need for input/output of data, the transfer of data is informed to a DMA circuit 1n. Then the circuit 1n sets a BREQ#n under an enable state. An exclusive bus request scan circuit 50 finds out that the exclusive bus request is enable at a time point when the BREQ#n is scanned and requests the evacuation of a bus 40 to a processor 20. Then the processor 20 informs the evacuation of the bus 40 to the circuit 50 and gives permission to the circuit 1n for the use of the bus 40 to perform the transfer of data between the device 6n and a memory 30. When the transfer of data is through, the processor 20 starts access to the bus 40 and starts again the scan of the BREQ which is temporarily discontinued.