PURPOSE: To set an output in a high speed, by providing a preset circuit at the connection point between the first and the second transistors (TRs) and presetting the potential of this connection point to the potential between the first and the second electric power sources during the read reference period of stored information.

CONSTITUTION: A MOS TR QN2 is connected between the common connection point of MOS TRs QP1 and QN1 and an electric power source VDD, and a MOS TR QP2 is connected between the common connection point and a ground point VSS, and the substrate potential of the TR QN2 is connected to the ground point VSS, and the substrate potential of the TR QP2 is connected to the power source VDD. Said TRs QN2 and QP2 constitute the preset circuit which sets the potential of the common connection point of TRs QP1 and QN1 to a middle potential between the level of the power source VDD and the level of the ground point VSS, and the conduction of these TRs QN2 and QP2 is controlled by a controlling means consisting of inverters NOT6 and NOT7, an NOR gate NOR2, and an NAND gate NAND2. Therefore, an output signal Vout' is changed from the middle level between VDD and VSS to the level of VDD or VSS, and the output is set in a high speed.