Title:
CALCULATION CIRCUIT, CALCULATION DEVICE, INFORMATION PROCESSING DEVICE, AND GROUND STATE SEARCH METHOD FOR ISING MODEL
Document Type and Number:
WIPO Patent Application WO/2021/084629
Kind Code:
A1
Abstract:
This calculation circuit is provided with: spin memory for storing a value indicating the state of one spin of an interaction model; interaction coefficient auxiliary memory for storing an interaction coefficient of a subfunction so as to correspond to the spin memory; external magnetic field coefficient auxiliary memory for storing an external magnetic field coefficient of the subfunction so as to correspond to the spin memory; a weight input line for receiving a weight signal of the subfunction; an interaction coefficient calculation unit that calculates a weighted subfunction interaction coefficient using the weight signal of the subfunction and the interaction coefficient of the subfunction; an external magnetic field coefficient calculation unit that calculates a weighted subfunction external magnetic field coefficient using the weight signal of the subfunction and the external magnetic field coefficient of the subfunction; and a next state calculation unit that calculates the next state of spin on the basis of the value indicating the state of spin, the weighted subfunction interaction coefficient, and the weighted subfunction external magnetic field coefficient.
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Inventors:
OKUYAMA TAKUYA (JP)
YAMAOKA MASANAO (JP)
YAMAOKA MASANAO (JP)
Application Number:
PCT/JP2019/042433
Publication Date:
May 06, 2021
Filing Date:
October 29, 2019
Export Citation:
Assignee:
HITACHI LTD (JP)
International Classes:
G06N99/00
Domestic Patent References:
| WO2016006071A1 | 2016-01-14 |
Foreign References:
| JP2016051313A | 2016-04-11 |
Other References:
KANAMARU, S. ET AL.: "Efficient Ising Model Mapping to Solving Slot Placement Problem", PROCEEDINGS OF THE 2019 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS (ICCE, 13 January 2019 (2019-01-13), pages 1 - 6, XP033528076, ISBN: 978-1-5386-7910-4, DOI: 10.1109/ICCE.2019.8661947
YAMAOKA, M. ET AL.: "A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 51, no. 1, 9 December 2015 (2015-12-09), pages 303 - 309, XP011596430, ISSN: 0018-9200, DOI: 10.1109/JSSC. 2015. 2498601
KANAMARU, S. ET AL.: "Method to solve Slot Placement Problem by Ising Computer", IEICE TECHNICAL REPORT, vol. 118, no. 85, 7 June 2018 (2018-06-07), pages 161 - 166, ISSN: 0913-5685
YAMAOKA, M. ET AL.: "A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 51, no. 1, 9 December 2015 (2015-12-09), pages 303 - 309, XP011596430, ISSN: 0018-9200, DOI: 10.1109/JSSC. 2015. 2498601
KANAMARU, S. ET AL.: "Method to solve Slot Placement Problem by Ising Computer", IEICE TECHNICAL REPORT, vol. 118, no. 85, 7 June 2018 (2018-06-07), pages 161 - 166, ISSN: 0913-5685
Attorney, Agent or Firm:
SEIRYO I.P.C. (JP)
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