Title:
CIRCUIT BOARD FOR SEMICONDUCTOR PACKAGE AND METHOD FOR PRODUCING SAME
Document Type and Number:
WIPO Patent Application WO/2014/024754
Kind Code:
A1
Abstract:
(1) A solder resist is formed on a surface of a wiring substrate obtained by forming through holes and wiring patterns to an insulating substrate; (2) blind vias are formed in the solder resist on a semiconductor chip mounting side by laser, each via having a diameter of 100 μm or smaller; (3) an electroless plated coating is formed on a surface of the solder resist on the semiconductor chip mounting side having the blind vias; (4) the blind vias of the solder resist having the electroless plated coating formed on the surface thereof are subjected to via filling by electrolytic plating whereby electrolytic plated layers are formed with respect to the blind vias; and (5) the electrolytic plated layers and the electroless plated coating are removed by etching from areas other than the blind vias on the surface of the solder resist on the semiconductor chip mounting side, so that the solder resist is exposed, whereby a surface connection pad formed with the electrolytic plated layer and the electroless plated coating is formed in each blind via.
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Inventors:
OKAMOTO HIDEKI (JP)
KAWAI YOSHIHARU (JP)
OOCHI TOMOYA (JP)
SUGIMOTO FUTOSHI (JP)
TAKII YOJI (JP)
KAWAI YOSHIHARU (JP)
OOCHI TOMOYA (JP)
SUGIMOTO FUTOSHI (JP)
TAKII YOJI (JP)
Application Number:
PCT/JP2013/070783
Publication Date:
February 13, 2014
Filing Date:
July 31, 2013
Export Citation:
Assignee:
MITSUBISHI GAS CHEMICAL CO (JP)
JAPAN CIRCUIT IND COMPANY LTD (JP)
JAPAN CIRCUIT IND COMPANY LTD (JP)
International Classes:
H01L23/12; H05K3/46
Domestic Patent References:
| WO2005076682A1 | 2005-08-18 |
Foreign References:
| JP2001110940A | 2001-04-20 | |||
| JP2000244125A | 2000-09-08 | |||
| JP2003046243A | 2003-02-14 | |||
| JP2004327744A | 2004-11-18 |
Attorney, Agent or Firm:
AOKI, Atsushi et al. (JP)
Aoki 篤 (JP)
Aoki 篤 (JP)
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