Title:
CLOCK CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY
Document Type and Number:
WIPO Patent Application WO/2024/000811
Kind Code:
A1
Abstract:
Disclosed in the embodiments of the present disclosure are a clock control circuit and a semiconductor memory. The clock control circuit comprises a first decoding path, a second decoding path and a clock gating circuit, wherein the first decoding path is configured to receive an initial command signal and an initial clock signal, and shift and decode the initial command signal under the trigger of the initial clock signal to obtain and output a first decoded signal; the second decoding path is configured to receive the initial command signal, and decode the initial command signal to obtain and output a second decoded signal, a leading edge of the second decoded signal being ahead of a leading edge of the first decoded signal; and the clock gating circuit is used for receiving the initial clock signal, the first decoded signal and the second decoded signal, and is used for performing, according to the first decoded signal and the second decoded signal, gating on the initial clock signal to output a clock gating signal.
Inventors:
ZHANG HONGGUANG (CN)
Application Number:
PCT/CN2022/117578
Publication Date:
January 04, 2024
Filing Date:
September 07, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C29/12; G11C29/14
Foreign References:
| GB2011229A | 1979-07-04 | |||
| US11211103B1 | 2021-12-28 | |||
| US20030021368A1 | 2003-01-30 | |||
| US4085288A | 1978-04-18 | |||
| CN114678056A | 2022-06-28 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
Download PDF: