Title:
CLOCK GENERATION CIRCUIT, AND COMMUNICATION DEVICE
Document Type and Number:
WIPO Patent Application WO/2006/009159
Kind Code:
A1
Abstract:
A clock generation circuit enabled to adjust the quantity of diffusion of a desired spectrum easily and reduced in unnecessary radiation. A clock generation circuit (100) comprises a PLL circuit (60) and a jitter addition circuit (20). The jitter addition circuit (20) generates a bias current for driving a voltage-controlled oscillator (16) of the PLL circuit (60), and adds fluctuations. This jitter addition circuit (20) includes an oscillator (22) and a current source (24) so that the fluctuation components generated by the oscillator (22) are added to the bias current. The oscillation frequency of the oscillator (22) is several times as high as the natural number of the frequency of an input clock signal (CKIN).
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Inventors:
SUGIMOTO YASUHITO (JP)
Application Number:
PCT/JP2005/013280
Publication Date:
January 26, 2006
Filing Date:
July 20, 2005
Export Citation:
Assignee:
ROHM CO LTD (JP)
SUGIMOTO YASUHITO (JP)
SUGIMOTO YASUHITO (JP)
International Classes:
G06F1/04; H03K7/04; H03L7/099; H03L7/18; (IPC1-7): H03K7/04; G06F1/04; H03L7/099; H03L7/18
Foreign References:
| JP2003332997A | 2003-11-21 | |||
| JP2001230667A | 2001-08-24 | |||
| JP2001168644A | 2001-06-22 |
Attorney, Agent or Firm:
Morishita, Sakaki (Ebisu-Nishi Shibuya-ku Tokyo, 21, JP)
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