Title:
FIELD EFFECT TRANSISTOR
Document Type and Number:
WIPO Patent Application WO/2024/042814
Kind Code:
A1
Abstract:
This field effect transistor suppresses the dielectric breakdown of a gate insulating film when a current diffusion n-layer is provided. The field effect transistor includes: a semiconductor substrate having a trench in the upper face thereof; a gate insulating film; and a gate electrode. The semiconductor substrate includes a p-type body layer and a lower n-layer disposed below the body layer. The lower n-layer includes: a current diffusion n-layer that is in contact with the body layer from below; and a low concentration n-layer that is in contact with the current diffusion n-layer from below and has an n-type impurity concentration which is lower than that of the current diffusion n-layer. The inner faces of the trench include: a side face that is constituted by a surface having a radius of curvature of 0.7 µm or greater; and a bottom connection face that connects the side face and the lower end of the trench and that is constituted by a concave curved face having a radius of curvature of less than 0.7 µm. The portion of the current diffusion n-layer having the peak value is in contact with the gate insulating film at the side face.
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Inventors:
TAKAYA HIDEFUMI (JP)
Application Number:
PCT/JP2023/021200
Publication Date:
February 29, 2024
Filing Date:
June 07, 2023
Export Citation:
Assignee:
DENSO CORP (JP)
International Classes:
H01L29/78
Domestic Patent References:
| WO2022137788A1 | 2022-06-30 |
Foreign References:
| JP2021182639A | 2021-11-25 | |||
| JP2020031157A | 2020-02-27 | |||
| JP2022002345A | 2022-01-06 | |||
| JP2008016747A | 2008-01-24 | |||
| JP2011253837A | 2011-12-15 |
Attorney, Agent or Firm:
KAI-U PATENT LAW FIRM (JP)
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