Technical Field Embodiments of the present invention relate to an instruction provider for providing a sequence of instructions and a corresponding method. Further embodiments of the present invention relate to a test processor for providing a device under test signal for a device under test and a corresponding method. Further embodiments of the present invention relate to a test system comprising such a test processor and a dictionary memory structure.

Background of the Invention

In conventional test systems a run length encoding (RLE) algorithm is used to compress vector data of a pattern to reduce the tester (sequencer) memory footprint of the test pattern. The compression can be done by the software (or user) and the decompression can be done by a test processor sequencer program. Conventional RLE algorithms can only compress the data if there is a consecutive repeating pattern in the program. In some cases (such as pseudo random bit sequences - PRBS) the data has no consecutive repeating sequences. A test program can be huge in size (for example even larger than 200 MB) and sometimes cannot be even loaded into a tester memory. Furthermore, a further growth of such test programs is expected for the future.

Figs. 7a-d show an example how a conventional run length encoding algorithm is performed.

A sequence of data as shown in Fig. 7 having the length of 18 is assumed. For reasons of simplicity it is assumed that all blocks have the same length. Using a conventional run length encoding algorithm this sequence in Fig. 7a can be compressed to the sequence shown in Fig. 7b having the length 9, and thereby achieving a compression factor of 2. But when the data looks like shown in Fig. 7c, it can only be compressed to the sequence shown in Fig. 7d having a length of 16.

Summary of the Invention It is an objective of the present invention to provide a concept which enables the provision of a more efficient sequence of instructions.

This objective is solved by the subject matter of the independent claims. Embodiments of the present invention provide an instruction provider for providing a sequence of instructions based on a representation of a sequence of test vectors. Each instruction defines the provision of at least one test vector to a device under test. The instruction provider is configured to identify in the representation of the sequence of test vectors subsequences of test vectors which occur at least two times in the sequence of test vectors. Furthermore, the instruction provider is configured to store the identified subsequences in a dictionary memory structure. Furthermore, the instruction provider is configured to provide the sequence of instructions such that the sequence of instructions comprises at least a first instruction defining a first provision of a first subsequence of test vectors stored in the dictionary memory structure and such that the sequence of instructions comprises a second instruction defining a second provision of the first subsequence. The first instruction and the second instruction reference to the same (first) entry of the dictionary memory structure.

It has been found by the inventors that an improved concept for providing a sequence of instructions can be provided, when a representation of a sequence of test vectors based on which a sequence of instructions is provided is scanned for subsequences which occur more than twice (which occur repeatedly) without the need for having these subsequences occurring subsequently. The subsequences which occur more than twice can be stored in a dictionary memor structure so that in the sequence of instructions different instructions can reference to the same entry of the dictionary memory structure to provide the subsequence of test vectors to the device under test. Hence, it has been found by the inventors that in some cases (such as PRBS - Pseudorandom Bit Sequence) the data has no consecutive repeating sequence but subsequences of data (the subsequences of test vectors), which are randomly distributed (and repeated) throughout the pattern. To now achieve a more efficient compression algorithm those subsequences in a pattern (in the sequence of test vectors) are identified and a hybrid algorithm, which consists of a method RLE (Run Length Encoding) and a dictionary based encoding (like Lempel-Ziv) is used to compress the data. The instruction provider (e.g. implemented in software) arranges the vector data in a tester memory in a special layout (in the dictionary memory structure) and creates a suitable test processor (sequencer) program (the sequence of instructions) to decompress the data on the fly.

Accordingly, embodiments of the present invention provide a test processor which is capable of handling the sequence of instructions as provided by the instruction provider. Hence, embodiments of the present invention provide a test processor for providing a device under test signal for a device under test based on a sequence of instructions (such as a sequence of instructions provided by the instruction provider). The test processor is configured to obtain an entry of a dictionary memory structure, in response to a current instruction in the sequence of instructions. The entry represents a subsequence of test vectors (which could be identified and stored by the instruction provider into the dictionary memory structure). The test processor is further configured to provide the device under test signal based on the subsequence of test vectors.

Hence, the test processor according to embodiments of the present invention is configured to access the dictionary memory structure created by the instruction provider to obtain an entry which contains a subsequence of test vectors identified and stored by the instruction provider. Hence, several different instructions (in the sequence of instructions) which may occur subsequently in the sequence of instructions (but with further instructions in between) can reference to the same entry in this dictionary memory structure and therefore to the same subsequence of test vectors to be provided in the device under test signal. By having the special instructions and furthermore the dictionary memory structure it can be achieved that not for every occurrence of the subsequence of test vectors in the sequence of test vectors the complete subsequence has to be copied into the memory of the test processor or of a test system, as it is now sufficient to provide this subsequence of test vectors only one time (in the dictionary memory structure) and to provide corresponding instructions, which instruct the test processor to access the dictionary memory structure to obtain the subsequences of test vectors from the dictionary memory structure.

Hence, embodiments of the present invention provide dedicated test processor instructions to create an optimized memory layout and to efficiently decompress the data. To summarize, the vector data of the pattern (the test vectors of the representation of the sequence of test vectors) is laid out as an indexed dictionary (array) and the sequencer program (such as the instruction provider) configures the test processor to consider the memory region as such an indexed dictionary (as a dictionary memory structure). Later instruction can use an index to retrieve the data (the subsequence of test vectors) from the dictionary for the vector generation.

According to further embodiments of the present invention the instruction provider can be configured to provide the sequence of instructions such that the sequence of instructions comprises a third instruction defining the provision of a true subset of the first subsequence of test vectors.

Hence, it has also been found by the inventors that it is neither practical nor possible to find the most optimal compression considering other constraints like compression performance, memory bandwidth and throughput. Therefore, sometimes there are small subsequences that are contained in larger subsequences which cannot/should not be broken down to smaller pieces considering throughput. The instruction provider of embodiments of the present invention can find the smaller sequences and only keep the larger sequence in the dictionary memory structure. The smaller one can then be retrieved from the larger one to obtain a higher compression. In other words, an instruction does not necessarily define the complete provision of the complete subsequence of test vectors, but can also define the provision of only a true subset of a subsequence of test vectors stored in the dictionary memory structure. As an example, such an instruction can comprise an offset which defines a first test vector of the true subset and a length which defines the length and the last test vector of the true subset of test vectors.

Accordingly, the test processor can be configured to, in response to a further instruction (such as the mentioned third instruction) obtain a true subset of a subsequence of test vectors (such as the first subsequence of test vectors) stored in the dictionary memory structure. Furthermore, the test processor is configured to provide the device under test signal based on this true subset of the (first) subsequence of test vectors.

Hence, embodiment of the present invention achieve the eliminating of the storing of smaller subsequences of test vectors which are part of larger subsequences of test vectors which are already stored inside the dictionary memory structure.

With the concept of the present invention one can achieve a maximum throughput with a heavy compression.

Further embodiments of the present invention provide a method for providing a sequence of instructions based on a representation of a sequence of test vectors.

Further embodiments of the present invention provide a method for providing a device under test signal for a device under test based on a sequence of instructions.

Short Description of the Figures

Embodiments of the present invention will be described in more detail using the accompanying figures, in which:

Fig. 1 shows a block schematic diagram of an instruction provider according to an embodiment of the present invention; Fig. 2 shows a block schematic diagram of a test processor according to embodiment of the present invention;

Fig. 3 shows a first example of how the instruction provider shown in Fig. 1 performs the compression of a sequence of test vectors into a sequence of instructions;

Fig. 4 shows an example of how smaller subsequences which are part of larger subsequences of test vectors can be eliminated; Fig. 5 shows a flowchart of a method for providing a sequence of instructions based on a representation of a sequence of test vectors according to an embodiment of the present invention; Fig. 6 shows a flowchart of a method for providing a device under test signal for a device under test based on a sequence of instructions; and

Fig. 7 shows an example of how a conventional run length encoding algorithm works.

Detailed Description of Embodiments of the Present Invention

Before embodiments of the present invention are described in more detail it is to be pointed out that in the figures the same elements or functionally equal elements are provided with the same reference numbers. Hence, descriptions provided for elements having the same reference numbers are mutually exchangeable.

Fig. 1 shows a block schematic diagram of an instruction provider 100 according to an embodiment of the present invention. The instruction provider 100 is configured to provide a sequence 101 of instructions based on a representation 103 of a sequence of test vectors. Each instruction in the sequence of instructions 101 defines a provision of at least one test vector (of the representation 103 of the sequence of test vectors) to a device under test. The instruction provider 100 is configured to identify in the representation 103 of the sequence of test vectors subsequences of test vectors which occur at least two times in the representation 103 of the sequence of test vectors. Furthermore, the instruction provider 100 is configured to store the identified subsequence of test vectors in a dictionary memory structure 105. Furthermore, the instruction provider 100 is configured to provide the sequence of instructions such that the sequence of instructions comprises at least a first instruction defining a first provision of a first subsequence 107 of test vectors stored in the dictionary memory structure 105 and a second instruction defining a second provision of the first subsequence 107 of test vectors. Furthermore, the first instruction and the second instruction reference to the same (e.g. first) entry of the dictionary memory structure. The representation 103 of the sequence of test vectors can be, for example, a simple stream of test vectors. According to further embodiments the representation 103 of the sequence of test vectors could also be a part of a program code having loop instructions (which define the looping of certain subsequences of test vectors). Such subsequences of test vectors can be found by the instructions provider 100 in the representation 103 and are stored into the dictionary memory structure 105 as different entries.

The dictionary memory structure 107 can be, for example, a dedicated area in a program code generated together with the sequence 101 of instructions. This dictionary memory structure 105 generates a dictionary in a memory onto which a test processor (such as a test processor 200 shown in Fig. 2) can access, to obtain the different subsequences of test vectors stored in the dictionary memory structure 105. As an example, when a compiled binary which comprises the sequence 101 of instructions and furthermore the subsequences of test vectors is loaded onto a test processor 200, the test processor 200 generates in its associated test memory a dictionary comprising the subsequence of test vectors based on the dictionary memory structure 105.

An example of such a dictionary memory structure is given in Fig. 3b and will be explained later on.

Furthermore, the first entry of the dictionary memory structure 105 contains the first subsequence 107 of test vectors. In the example shown in Fig. 3b the first entry of the dictionary memory structure comprises the first subsequence 107 of test vectors, which in this case is the sequence of eight test vectors (00 F1 F3 E1 05 90 55 AA).

Furthermore, each of the test vectors in such a subsequence of test vectors defines the provision of a plurality of signal transitions or signal states in a device under test signal which is to be provided to the device under test. Hence, a signal wave which is provided to the device under test is typically based on the signal transitions or signal states defined in the sequence of test vectors. Furthermore, the instruction provider 100 can be configured to further store a plurality of subsequences of test vectors in the dictionary memory structure 105. Lengths of these different subsequences of test vectors stored in the dictionary memory structure 105 can vary. Hence, the instruction provider 100 can be configured to store a second subsequence 109 of test vectors in the dictionary memory structure 105, wherein a length of the first subsequence 07 is different from a length of the second subsequence 109. Referring again to the example of Fig. 3b it can be seen that the first subsequence 107 has (in this example) a length of 8 while the second subsequence 109 of test vectors has (in this example) a length of 6 test vectors. Hence, the length of the subsequences of test vectors stored in the dictionary memory structure 105 is not fix and typically depends on the representation 103 of the sequence of test vectors and on the length of the subsequences of test vectors in the representation 103 of test vectors which occur more than twice (which occur repeatedly).

As already described, the representation 103 of test vectors can be a stream of test vectors. The instruction provider 100 is configured to receive this stream of test vectors and to provide the sequence 101 of instructions based on this received stream of test vectors.

Such a stream of test vectors could be for example the one shown in Fig. 7a or the one shown in Fig. 7c in which A, B and C are each a block of test vectors.

Fig. 2 shows a block schematic diagram of a test system 200 according to an embodiment of the present invention. The test system 200 comprises a test processor 201 according to an embodiment of the present invention and a dictionary memory structure 105. The dictionary memory structure 105 could be a region in a memory of the test system 200 which could be even a memory of the test processor 201 itself. Such a memory could be, for example a volatile working memory of the test system 200. Furthermore, Fig. 2 shows a device under test 203, the device under test 203 is configured to receive a device under test signal 205 from the test processor 201. The test processor 201 is configured to provide the device under test signal 205 for the device under test 203 based on a sequence of instructions. The sequence of instructions is typically provided by the instruction provider 100 and therefore the sequence of instructions shown in Fig. 2 is also given the reference sign 101. The test processor 201 is configured to obtain an entry of the dictionary memory structure 105 in response to a current instruction in the sequence 101 of instructions. As already described, the entry represents a subsequence of test vectors (stored in the dictionary memory structure 105). Furthermore, the test processor 201 is configured to provide the device under test signal 205 based on the subsequence of test vectors obtained from the dictionary memory structure 105 in dependence on the current instruction. In other words, the test processor 201 obtains the subsequence of test vectors from the dictionary memory structure 105, wherein each test vector corresponds to a certain number of signal transitions or signal states of the device under test signal 205. Hence, the test processor 201 applies these signal states or signal transitions defined in the test vectors in the subsequence of test vectors to the device under test 203 by means of the device under test signal 205.

The dictionary memory structure 105 can be created in the memory of the test system 200, for example using dedicated test processor instructions which are provided by the instruction provider 100 inside the sequence 101 of instructions to create an optimized memory layout in the test system 200.

In the following, two examples are given to explain the present invention in more detail. Furthermore, further advantageous modifications of the test processor 201 and the instruction processor 100 will be described. Starting from the sequence of test vectors shown in Fig. 7c, with the new memory layout and the new test processor instructions described in this present application, a compression of the data to the stream shown in Fig. 3a can be achieved. Hence, a compression factor of 6 can be achieved. As already described the vector data of the pattern is laid out as an indexed dictionary (array) such as the dictionary memory structure 105 as shown in Fig. 3b. The sequencer or the test processor 201 is configured to consider the memory region in which the dictionary memory structure 105 is placed as such an indexed dictionary. Later instructions (the instructions in the sequence 101 of instructions) can use an index to retrieve the data (the several subsequences of test vectors) from the dictionary memory structure 105 for the vector generation (for the generation of the device under test signal 205).

As an example, the sequence of test vectors shown in Fig. 7c could create a dictionary memory structure 105 as shown in Fig. 3b. The exemplary dictionary memory structure 105 shown in Fig. 3b only has three entries, each of which defines the provision of a certain subsequence of test vectors in the device under test signal 205.

Fig. 3c shows an example for a sequencer program for providing the first entry (the first subsequence 107 of test vectors) and the second entry (the second subsequence 109 of test vectors). In the example shown in Fig. 3c, it can be seen that an instruction can further include a number of times a certain subsequence of test vectors is to be repeated subsequently. In the example shown in Figs. 3c the second subsequence 109 of test vectors (also designated as B) is generated twice.

As already described, each vector in a subsequence of test vectors defines a set of signal transition or signal states of the device under test signal 205. Furthermore, it has been found by the inventors that is neither practical nor possible to find the most optimal compression when considering constraints like compression performance, memory bandwidth and throughput. Therefore, there are sometimes small subsequences of test vectors that are contained in larger subsequences of test vectors which cannot or should not be broken down to smaller pieces when considering throughput.

The instruction provider 100 can find such smaller subsequences and only keep the larger entry (the larger subsequences of test vectors containing the smaller subsequences of test vectors). The smaller subsequence of test vectors can then be obtained from the larger one to obtain a higher compression.

Fig. 4a shows a dictionary memory structure 105 which is further compressed by eliminating the entry C altogether as it is already contained in the entry A. In other words, the instruction provider 100 is configured to, if it finds a subsequence of test vectors which is already contained in another (larger) subsequence of test vectors to not separately store the smaller subsequence of test vectors in the dictionary memory structure 105. To give the test processor 200 the possibility to obtain such smaller subsequences of test vectors a special instruction can be provided in the sequence 101 of instructions which can contain a value defining the entry in the dictionary memory structure 105 to be obtained and furthermore an offset and a length for the smaller subsequence of test vectors.

Such an example is shown in Fig. 4b in which in the second instruction the smaller subsequence of test vectors C which is completely included in the larger subsequence of test vectors A is obtained. As can be seen, these instructions for obtaining the subsequence of test vectors C comprises an offset value defining the first test vector of the smaller subsequence of test vectors inside the larger subsequence of test vectors and furthermore a length value defining the length of the smaller subsequence of test vectors inside the larger subsequence of test vectors. Hence, the sequence 101 of instructions can comprise an instruction which contains an index value defining a certain subsequence of test vectors stored in the dictionary memory 105 to which this instruction references. Furthermore, this instruction can comprise an offset values defining a first test vector of a true subset of test vectors (the subsequence C) in a certain subsequence of test vectors (the larger subsequence A). Furthermore, such instruction comprises a length or end value defining the last test vector of the true subset (the smaller subsequence C) in the certain subsequence of test vectors (the larger subsequence A).

Furthermore, as can be seen from Fig. 4a, the instruction provider 100 is configured to compare an identified subsequence of test vectors in the representation 103 of test vectors with the subsequences of test vectors already stored in the dictionary memory structure 105. If an identified subsequence is a true subset of an already stored subsequence (such as the subsequence C being a true subset of the subsequence A) the instruction provider 100 is configured to omit storing the identified subsequence. Instead, the instruction provider 100 provides in the sequence 101 of instructions an instruction defining a provision of the identified subset of test vectors as a true subset of the already stored subsequence.

This is done, for example, by providing the instruction as shown in Fig. 4b containing on the one hand an index value defining the entry in the dictionary memory structure 105 and on the other hand an offset value and a length or end value defining the true subset of test vectors of the subsequence of test vectors stored in the dictionary memory structure 105 at the index value in the instruction. Furthermore, the instruction provider 100 is further configured to, if an already stored subsequence in the dictionary memory structure 105 is a true subset of a newly identified subsequence, remove the already stored subset from the dictionary memory structure 105, store the newly identified subsequence in the dictionary memory structure 105 and to replace the instructions in the sequence 101 of instructions referencing to the already stored subset of test vectors in the dictionary memory structure 105 with instructions referencing to the newly identified subsequence of test vectors in the dictionary memory structure 105 and which further define the provision of the already stored subsequence of test vectors (which has been deleted in the dictionary memory structure 105) as a true subset of the newly identified subsequence of test vectors. In other words, when the instruction provider 100 identifies in the representation 103 of the sequence of test vectors a subsequence of test vectors which is a larger subsequence of test vectors than an already stored subsequence of test vectors but which completely contains the already stored subsequence of test vectors, the already stored subsequence of test vectors can be replaced with the newly identified subsequence of test vectors. Instructions in the sequence 101 of instructions, which reference to the smaller subsequence of test vectors are then replaced with instructions which reference to the newly identified (larger) subsequence of instructions and which furthermore define a provision of the smaller subset of instructions as a true subset of the larger subsequence of instructions.

By having this mechanism an optimized compression can be achieved.

Embodiments of the present invention can be implemented in hardware or software and achieve a very good compression for large patterns of various types.

Fig. 5 shows a flowchart of a method 500 according to an embodiment of the present invention.

The method 500 can be performed, for example, using the instruction provider 100.

The method 500 for providing a sequence of instructions based on a representation of a sequence of test vectors, each instruction defining the provision of at least one test vector to device under test comprises a step 501 of identifying in the representation of the sequence of test vectors subsequences of test vectors which occur at least two times in the representation of the sequence of test vectors.

Furthermore, the method 500 comprises a step 503 of storing the identified subsequences of test vectors in a dictionary memory structure. Furthermore, the method 500 comprises a step 505 of providing the sequence of instructions such that the sequence of instructions comprises at least a first instruction defining a first provision of a first subsequence of test vectors stored in the dictionary memory structure and a second instruction defining a second provision of the first subsequence. The first instruction and the second instruction reference to the same entry of the dictionary memory structure.

Furthermore, Fig. 6 shows a flowchart of a method 600 for providing a device under test signal for a device under test based on a sequence of instructions according to an embodiment of the present invention. The method 600 can be performed, for example, using the test processor 200.

The method 600 comprises a step 601 of obtaining an entry of a dictionary memory structure in response to a current instruction in the sequence of instructions. The entry represents a subsequence of test vectors stored in the dictionary memory structure.

Furthermore, the method 600 comprises a step 603 of providing the device under test signal based on the subsequence of test vectors.

The methods 500, 600 may be supplemented by any of the features and functionalities described herein with respect to the apparatus, and may be implemented using the hardware components of the apparatus.

Although some aspects have been described in the context of an apparatus, it is clear that these aspects also represent a description of the corresponding method, where a block or device corresponds to a method step or a feature of a method step. Analogously, aspects described in the context of a method step also represent a description of a corresponding block or item or feature of a corresponding apparatus. Some or ali of the method steps may be executed by (or using) a hardware apparatus, like for example, a microprocessor, a programmable computer or an electronic circuit. In some embodiments, some one or more of the most important method steps may be executed by such an apparatus.

Depending on certain implementation requirements, embodiments of the invention can be implemented in hardware or in software. The implementation can be performed using a digital storage medium, for example a floppy disk, a DVD, a Blue-Ray, a CD, a ROM, a PROM, an EPROM. an EEPROM or a FLASH memory, having electronically readable control signals stored thereon, which cooperate (or are capable of cooperating) with a programmable computer system such that the respective method is performed. Therefore, the digital storage medium may be computer readable.

Some embodiments according to the invention comprise a data carrier having electronically readable control signals, which are capable of cooperating with a programmable computer system, such that one of the methods described herein is performed.

Generally, embodiments of the present invention can be implemented as a computer program product with a program code, the program code being operative for performing one of the methods when the computer program product runs on a computer. The program code may for example be stored on a machine readable carrier.

Other embodiments comprise the computer program for performing one of the methods described herein, stored on a machine readable carrier.

In other words, an embodiment of the inventive method is, therefore, a computer program having a program code for performing one of the methods described herein, when the computer program runs on a computer.

A further embodiment of the inventive methods is, therefore, a data carrier (or a digital storage medium, or a computer-readable medium) comprising, recorded thereon, the computer program for performing one of the methods described herein. The data carrier, the digital storage medium or the recorded medium are typically tangible and/or non- transitionary.

A further embodiment of the inventive method is, therefore, a data stream or a sequence of signals representing the computer program for performing one of the methods described herein. The data stream or the sequence of signals may for example be configured to be transferred via a data communication connection, for example via the Internet.

A further embodiment comprises a processing means, for example a computer, or a programmable logic device, configured to or adapted to perform one of the methods described herein. A further embodiment comprises a computer having installed thereon the computer program for performing one of the methods described herein.

A further embodiment according to the invention comprises an apparatus or a system configured to transfer (for example, electronically or optically) a computer program for performing one of the methods described herein to a receiver. The receiver may, for example, be a computer, a mobile device, a memory device or the like. The apparatus or system may, for example, comprise a file server for transferring the computer program to the receiver .

In some embodiments, a programmable logic device (for example a field programmable gate array) may be used to perform some or all of the functionalities of the methods described herein. In some embodiments, a field programmable gate array may cooperate with a microprocessor in order to perform one of the methods described herein. Generally, the methods are preferably performed by any hardware apparatus.

The above described embodiments are merely illustrative for the principles of the present invention. It is understood that modifications and variations of the arrangements and the details described herein will be apparent to others skilled in the art. It is the intent, therefore, to be limited only by the scope of the impending patent claims and not by the specific details presented by way of description and explanation of the embodiments herein.