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Patent Searching and Data


Title:
MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
Document Type and Number:
WIPO Patent Application WO/2024/042609
Kind Code:
A1
Abstract:
Provided is a dynamic flash memory in which there are a semiconductor matrix p layer 1, an n+ layer 2 extends on one side thereof, and an n+ layer 3 is on the opposite side thereof in contact with the p layer 1, the p layer 1 is partially coated with a gate insulation layer 4, there is also a first gate conductor layer 5 in contact therewith, and, in contact with the gate insulation layer 4, the p layer 1 is partially coated with a gate insulation layer 6, and there is a second gate conductor layer 7 that is electrically separated from a gate electrode 5, and the n+ layer 2, the n+ layer 3, and the gate conductor layers 5, 7 are connected respectively to a source line, a bit line, a word line, and a plate line. During writing to the memory, after 1.0 V has been applied to the bit line, and after 1.5 V has been applied to the plate line, for example, 1.2 V is applied to the word line. The present invention is characterized in that during erasing of memory, after 2 V has been applied to the plate line, for example, the voltage applied to each terminal in the bit line is always a value such as 0.6 V that is no less than 0 V. In a memory read operation, after a voltage has been applied to the bit line, voltage is applied to the plate line and the word line in the stated order, and memory information is read.

Inventors:
KAKUMU MASAKAZU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
Application Number:
PCT/JP2022/031700
Publication Date:
February 29, 2024
Filing Date:
August 23, 2022
Export Citation:
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Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
KAKUMU MASAKAZU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
International Classes:
H10B12/00
Domestic Patent References:
WO2022137563A12022-06-30
WO2022168219A12022-08-11
Foreign References:
US20200135863A12020-04-30
JP2003188279A2003-07-04
JP2008147514A2008-06-26
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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