MEMORY TRANSISTOR, FABRICATION METHOD THEREOF AND SEMICONDUCTOR DEVICE

Title:

MEMORY TRANSISTOR, FABRICATION METHOD THEREOF AND SEMICONDUCTOR DEVICE

Document Type and Number:

WIPO Patent Application WO/2019/080850

Kind Code:

A1

Abstract:

A memory transistor comprises a substrate comprising a first surface and a second surface opposing the first surface, the substrate further comprising a first trench having an opening formed in the first surface; a first dielectric layer formed on an inner surface of the first trench; a gate layer formed on the first dielectric layer in the first trench, the gate layer having a top surface lower than the first surface; and a second dielectric layer filled in the first trench and located on the top surface of the gate layer, the second dielectric layer covering the gate layer and connecting to the first dielectric layer, the second dielectric layer having a cavity formed therein.

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Inventors:

ZHU RONGFU (CN)
LIN DINGYOU (CN)

Application Number:

PCT/CN2018/111535

Publication Date:

May 02, 2019

Filing Date:

October 24, 2018

Export Citation:

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Assignee:

CHANGXIN MEMORY TECH INC (CN)

International Classes:

H01L29/788

Foreign References:

CN107634103A	2018-01-26
CN207320123U	2018-05-04
CN106992156A	2017-07-28
US20150311276A1	2015-10-29
CN106952919A	2017-07-14
US20120049266A1	2012-03-01
CN102543944A	2012-07-04

Attorney, Agent or Firm:

SHANGHAI SAVVY INTELLECTUAL PROPERTY AGENCY (CN)

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